[Proj 3] Concatenating bits in structural Verilog

[Alexander Robin Cohn Wallisch]

Say I have two 16-bit inputs that I want to concatenate into a single
32-bit output. In behavorial Verilog, I say "output = {in1, in2};"
Does anybody know how I do this in structural Verilog? Thanks.

Alex

[Andrew Schultz]

You are allowed to use {} as a concatenation operator for the project.
However, to keep things in the spirit of structural verilog, you can
only use this to concatenate things as an input to a block or gate. For
example, say I want to do an add and concatenate values together, you
can do:

wire [15:0] foo, bar;
wire [31:0] result, blah;

add32 adder(.S(result), .A({foo, bar}), .B(blah));

In other words, you are not allowed to do "wire foo = {bar, blah};" but
you can concatenate as things are going into a module or gate.

-Andrew

Post by Alexander Robin Cohn Wallisch
Say I have two 16-bit inputs that I want to concatenate into a single
32-bit output. In behavorial Verilog, I say "output = {in1, in2};"
Does anybody know how I do this in structural Verilog? Thanks.
Alex

[Andrew Schultz]

You are allowed to use {} as a concatenation operator for the project.
However, to keep things in the spirit of structural verilog, you can
only use this to concatenate things as an input to a block or gate. For
example, say I want to do an add and concatenate values together, you
can do:

wire [15:0] foo, bar;
wire [31:0] result, blah;

add32 adder(.S(result), .A({foo, bar}), .B(blah));

In other words, you are not allowed to do "wire foo = {bar, blah};" but
you can concatenate as things are going into a module or gate.

-Andrew

Post by Alexander Robin Cohn Wallisch
Say I have two 16-bit inputs that I want to concatenate into a single
32-bit output. In behavorial Verilog, I say "output = {in1, in2};"
Does anybody know how I do this in structural Verilog? Thanks.
Alex

[Udam Saini]

suppose x and y are 32 bit wires:

so if we do add32 adder(.S(result), .A({x[16:0], y[16:0]}), .B(blah));
that is still considered structural right?.

[[TA] Andrew Schultz]

Yeah, that is fine too. You can use it for any width bus of wires.
Just make sure it isn't used in an assign or "wire =" statement. Only
structural statements.

Andrew

Post by Udam Saini
so if we do add32 adder(.S(result), .A({x[16:0], y[16:0]}), .B(blah));
that is still considered structural right?.